Ideal circuit

This circuit operates by passing a current that charges or discharges the capacitor ${\displaystyle C_{\text{F}}}$ during the time under consideration, which strives to retain the virtual ground condition at the input by off-setting the effect of the input current:

Referring to the above diagram, if the op-amp is assumed to be ideal, then the voltage at the inverting (-) input is held equal to the voltage at the non-inverting (+) input as a virtual ground. The input voltage passes a current ${\displaystyle V_{\text{in}}/{R_{1}}}$ through the resistor producing a compensating current flow through the series capacitor to maintain the virtual ground. This charges or discharges the capacitor over time. Because the resistor and capacitor are connected to a virtual ground, the input current does not vary with capacitor charge, so a linear integration that works across all frequencies is achieved (unlike RC circuit § Integrator).

The circuit can be analyzed by applying Kirchhoff's current law at the inverting input:

${\displaystyle i_{\text{1}}=I_{\text{B}}+i_{\text{F}}}$

For an ideal op-amp, ${\displaystyle I_{\text{B}}=0}$ amps, so:

${\displaystyle i_{\text{1}}=i_{\text{F}}}$

Furthermore, the capacitor has a voltage-current relationship governed by the equation:

${\displaystyle i_{\text{F}}=C_{\text{F}}{\frac {d(V_{\text{2}}-V_{\text{o}})}{dt}}}$

Substituting the appropriate variables:

${\displaystyle {\frac {V_{\text{in}}-V_{\text{2}}}{R_{\text{1}}}}=C_{\text{F}}{\frac {d(V_{\text{2}}-V_{\text{o}})}{dt}}}$

For an ideal op-amp, ${\displaystyle V_{2}=0}$ volts, so:

${\displaystyle {\frac {V_{\text{in}}}{R_{\text{1}}}}=-C_{\text{F}}{\frac {dV_{\text{o}}}{dt}}}$

Integrating both sides with respect to time:

${\displaystyle \int _{0}^{t}{\frac {V_{\text{in}}}{R_{\text{1}}}}\ dt\ =-\int _{0}^{t}C_{\text{F}}{\frac {dV_{\text{o}}}{dt}}\,dt}$

If the initial value of ${\displaystyle V_{\text{o}}}$ is assumed to be 0 volts, the output voltage will simply be proportional to the integral of the input voltage:^[2]

${\displaystyle V_{\text{o}}=-{\frac {1}{R_{\text{1}}C_{\text{F}}}}\int _{0}^{t}V_{\text{in}}\,dt}$

Practical circuit

This practical integrator attempts to address a number of flaws of the ideal integrator circuit:

Real op-amps have a finite open-loop gain, an input offset voltage ${\displaystyle (V_{\text{OS}})}$ and input bias currents ${\displaystyle (I_{\text{B}})}$, which may not be well-matched and may be distinguished as ${\displaystyle I_{\text{B-}}}$ going into the inverting input and ${\displaystyle I_{\text{B+}}}$ going into the non-inverting input. This can cause several issues for the ideal design; most importantly, if ${\displaystyle V_{\text{in}}=0}$, both the output offset voltage and the input bias current ${\displaystyle I_{\text{B-}}}$ can cause current to pass through the capacitor, causing the output voltage to drift over time until the op-amp saturates. Similarly, if ${\displaystyle V_{\text{in}}}$ were a signal centered about zero volts (i.e. without a DC component), no drift would be expected in an ideal circuit, but may occur in a real circuit.

To negate the effect of the input bias current, it is necessary for the non-inverting terminal to include a resistor ${\displaystyle R_{\text{om}}=R_{1}||R_{\text{F}}||R_{\text{L}},}$ which simplifies to ${\displaystyle R_{1}}$ provided that ${\displaystyle R_{1}}$ is much smaller than the load resistance ${\displaystyle R_{L}}$ and the feedback resistance ${\displaystyle R_{F}}$. Well-matched input bias currents then cause the same voltage drop of ${\displaystyle R_{1}I_{\text{B}}}$ at both the inverting and non-inverting terminals, to effectively cancel out the effect of bias current at those inputs. A CMOS op amp should be selected to minimize errors from input bias current,^[3] since MOSFET gates don't require DC current and only have small leakage current on the order of picoamps (pA).^[4]

Also, in a DC steady state, an ideal capacitor acts as an open circuit. The DC gain of the ideal circuit is therefore infinite (or in practice, the open-loop gain of a non-ideal op-amp). Any DC (or very low frequency) component may then cause the op amp output to drift into saturation.^[5] To prevent this, the DC gain can be limited to a finite value by inserting a large resistor ${\displaystyle R_{\text{F}}}$ in parallel with the feedback capacitor. Note that some op amps have a large internal feedback resistor, and many real capacitors have leakage that is effectively a large feedback resistor.^[6]

The addition of these resistors turns the output drift into a finite, preferably small, DC error voltage:

${\displaystyle V_{\text{error}}=\left({\frac {R_{\text{F}}}{R_{1}}}+1\right)\left(V_{\text{OS}}+I_{\text{B-}}\left(R_{\text{F}}\parallel R_{1}\right)\right).}$

There are other methods, which may be combined, to deal with offset error. A variation of this circuit simply uses an adjustable voltage source instead of ${\displaystyle R_{\text{om}}}$ and some op amps with very low offset voltage may not even require offset correction.^[3] Offset correction is a bigger concern for older op amps, particularly BJT types. Another variation circuit to avoid offset correction that works for AC signals only is to capacitively-couple the input with a large input capacitor before ${\displaystyle R_{1}}$ which will naturally charge up to the offset voltage. Additionally, because offset may drift over time and temperature, some op amps provide null offset pins, which can be connected to a potentiometer whose wiper connects to the negative supply to allow readjusting when conditions change.^[6] It should also be noted that the integrator is commonly used as part of a feedback/servo loop which provides the DC feedback path, removing the need for a feedback resistor.^[3]

Ideal integrator

The ideal integrator's transfer function ${\displaystyle {\tfrac {1}{s}}}$ corresponds to the time-domain integration property of the Laplace transform. Since its denominator is just ${\displaystyle s}$, the transfer function has a pole frequency at ${\displaystyle f{=}0}$. Thus its frequency response has a steady -20 dB per decade slope across all frequencies and appears as a downward-sloping line in a Bode plot.

Practical integrator

The practical integrator's feedback resistor ${\displaystyle R_{F}}$ in parallel with the feedback capacitor ${\displaystyle C_{\text{F}}}$ turns the circuit into an active low-pass filter with a pole at the -3 dB cutoff frequency:

${\displaystyle f_{\text{cutoff}}={\frac {1}{{2\pi }{R_{\text{F}}}{C_{\text{F}}}}}\,.}$

The frequency response has a relatively constant gain up to ${\displaystyle f_{\text{cutoff}}}$, and then decreases by 20 dB per decade. While this circuit is no longer an integrator for low frequencies around and below ${\displaystyle f_{\text{cutoff}}}$, the error is decreases to only 0.5% at one decade above ${\displaystyle f_{\text{cutoff}}}$ and the response approaches that of an ideal integrator as the frequency increases.^[5] Real op amps also have a limited gain-bandwidth product (GBWP), which adds an additional high frequency pole. Integration only occurs along the -20 dB per decade slope, which is steady only from frequencies about a decade above ${\displaystyle f_{\text{cutoff}}}$ to about a decade below the op amp's GBWP.^[3]