Adapteva was founded in 2008 with the goal of bringing a ten times advancement in floating-pointperformance per watt for the mobile device market. Products are based on its Epiphany multi-core multiple instruction, multiple data (MIMD) architecture and its Parallella Kickstarter project promoting "a supercomputer for everyone" in September 2012. The company's original name, Adapteva, is a combination of "adapt" and the Hebrew word "Teva" meaning nature.
Sometime before October 2023 the company was renamed to Zero ASIC,[3] with a distinct focus on chiplet-based products and FPGA design tools.[4]
History
Adapteva was founded in March 2008, by Andreas Olofsson. The company was founded with the goal of bringing a 10× advancement in floating-point processing energy efficiency for the mobile device market. In May 2009, Olofsson had a prototype of a new type of massively parallel multi-core computer architecture. The initial prototype was implemented in 65nm and had 16 independent microprocessor cores. The initial prototypes enabled Adapteva to secure US$1.5 million in series-A funding from BittWare, a company from Concord, New Hampshire, in October 2009.[5]
Adapteva's first commercial chip product started sampling to customers in early May 2011 and they soon thereafter announced the capability to put up to 4,096 cores on a single chip.[citation needed]
The EpiphanyIII, was announced in October 2011 using 28nm and 65nm manufacturing processes.[citation needed]
Products
Epiphany CPUs
Adapteva's main product family is the Epiphany scalable multi-core MIMD architecture. The Epiphany architecture could accommodate chips with up to 4,096 RISCout-of-ordermicroprocessors, all sharing a single 32-bit flat memory space. Each RISC processor in the Epiphany architecture is superscalar with 64× 32-bit unified register file (integer or single-precision) microprocessor operating up to 1GHz and capable of 2GFLOPS (single-precision). Epiphany's RISC processors use a custom instruction set architecture (ISA) optimised for single-precision floating-point,[6] but are programmable in high level ANSI C using a standard GNU-GCC tool chain. Each RISC processor (in current implementations; not fixed in the architecture) has 32KB of local memory. Code (possibly duplicated in each core) and stack space should be in that local memory; in addition (most) temporary data should fit there for full speed. Data can also be used from other processor cores local memory at a speed penalty, or off-chip RAM with much larger speed penalty.
The memory architecture does not employ explicit hierarchy of hardware caches, similar to the Sony/Toshiba/IBM Cell processor, but with the additional benefit of off-chip and inter-core loads and stores being supported (which simplifies porting software to the architecture). It is a hardware implementation of partitioned global address space.[citation needed]
This eliminated the need for complex cache coherency hardware, which places a practical limit on the number of cores in a traditional multicore system. The design allows the programmer to leverage greater foreknowledge of independent data access patterns to avoid the runtime cost of figuring this out. All processor nodes are connected through a network on chip, allowing efficient message passing.[7]
Scalability
The architecture is designed to scale almost indefinitely, with 4 e-links allowing multiple chips to be combined in a grid topology, allowing for systems with thousands of cores.
Coprocessors
16-core Adapteva Epiphany chip, E16G301, from Parallella single-board computer
On August 19, 2012, Adapteva posted some specifications and information about Epiphany multi-core coprocessors.[8]
In September 2012, a 16-core version, the Epiphany-III (E16G301), was produced using 65nm[11] (11.5mm2, 500MHz chip[12]) and engineering samples of 64-core Epiphany-IV (E64G401) were produced using 28nm GlobalFoundries process (800MHz).[13]
The primary markets for the Epiphany multi-core architecture include:
Parallella single-board computer with 16-core Epiphany chip and Zynq-7010 FPGA
In September 2012, Adapteva started project Parallella on Kickstarter, which was marketed as "A Supercomputer for everyone." Architecture reference manuals for the platform were published as part of the campaign to attract attention to the project.[14] The US$750,000 funding goal was reached in a month, with a minimum contribution of US$99 entitling backers to obtain one device; although the initial deadline was set for May 2013, the first single-board computers with 16-core Epiphany chip were finally shipped in December 2013.[15]
Size of board is planned to be 86mm ×53mm (3.4in ×2.1in).[16][17][18]
The Kickstarter campaign raised US$898,921.[19][20] Raising US$3 million goal was unsuccessful, so no 64-core version of Parallella will be mass-produced.[21] Kickstarter users having donated more than US$750 will get "parallella-64" variant with 64-core coprocessor (made from initial prototype manufacturing with 50 chips yield per wafer).[22]
By 2016, the firm had taped out a 1024-core 64-bit variant of their Epiphany architecture that featured: larger local stores (64KB), 64-bit addressing, double-precision floating-point arithmetic or SIMD single-precision, and 64-bit integer instructions, implemented in the 16nm process node.[23] This design included instruction set enhancements aimed at deep-learning and cryptography applications. In July 2017, Adapteva's founder became a DARPAMTO program manager[24] and announced that the Epiphany V was "unlikely" to become available as a commercial product.[25]
Performance
The 16-core Parallella achieves roughly 5.0GFLOPS/W, and the 64-core Epiphany-IV made with 28nm estimated as 50GFLOPS/W (single-precision),[26] and 32-board system based on them achieves 15 GFLOPS/W.[27] For comparison, top GPUs from AMD and Nvidia reached 10 GFLOPS/W for single-precision in 2009–2011 timeframe.[28]
↑Andrew Back, Introducing the $99 Linux SupercomputerArchived November 17, 2015, at the Wayback Machine, Linux.com, January 24, 2013: "pledges of $99 or more being rewarded with at least one board with a 16-core device. ... The 16-core Epiphany chip delivers 26GFLOPS of performance and with the entire Parallella computer consuming only 5 watts"
↑64-core version of the Parallella board now offered! // Adapteva blog at Kickstarter, October 25, 2012: "The Epiphany-IV (64+2) core Parallella board will be offered for pledges above $750. ... the fact that we only get 50 dies per wafer for these initial prototype runs. We can't disclose wafer pricing and yields at 28nm,"
.png)
.png)