Double Data Rate 5 Synchronous Dynamic Random-Access Memory (DDR5 SDRAM) is a type of synchronous dynamic random-access memory. Compared to its predecessor DDR4 SDRAM, DDR5 was planned to reduce power consumption, while doubling bandwidth.[5] The standard, originally targeted for 2018,[6] was released on July 14, 2020.[2]
A new feature called Decision Feedback Equalization (DFE) enables input/output (I/O) speed scalability for higher bandwidth and performance improvement. DDR5 has about the same 14nslatency as DDR4 and DDR3.[7] DDR5 octuples the maximum dual in-line memory module (DIMM) capacity from 64GB to 512GB.[3][8] DDR5 also has higher frequencies than DDR4, up to 9.6 GT/s is currently possible, 8.2 GT/s translates into around 64 GB/s of bandwidth. Speeds of more than 13 GT/s have been achieved using liquid nitrogen cooling.[9]
Rambus announced a working DDR5 DIMM in September 2017.[10][11] On November 15, 2018, SK Hynix announced completion of its first DDR5 RAM chip; running at 5.2GT/s at 1.1V.[12] In February 2019, SK Hynix announced a 6.4GT/s chip, the highest speed specified by the preliminary DDR5 standard.[13] The first production DDR5 DRAM chip was officially launched by SK Hynix on October 6, 2020.[14][15]
Compared to DDR4, DDR5 further reduces memory voltage to 1.1V, a reduction from the 1.2 V required by DDR4. DDR5 modules incorporate on-board voltage regulators in order to reach higher speeds.[11][failed verification][17]
In 2024 the first CUDIMM (clocked unbuffered DIMM) and CSODIMM (clocked SODIMM) modules were introduced together with Intel Arrow Lake. These modules include a component to re-drive the clock signal to help reach higher speeds.[18] AMD does not support CUDIMM, though Zen 5 will accept CUDIMMs in bypass mode.
In 2026 ASRock and Intel released the DDR5 HUDIMM (half unbuffered DIMM) modules, it populating one 32-bit subchannel per DIMM, designed for budget but reduced-performance computer markets.[19] It requires the UEFI/BIOS to support HUDIMM.
Features
On-die ECC
Unlike DDR4, all DDR5 chips have on-die error-correction code, that detects and corrects storage errors before forwarding data to the CPU, to improve reliability and allow denser RAM chips with higher per-chip defect rate to be used.[20]
On-die ECC happens at a lower level than true ECC memory. It doesn't have extra chips and data lines to the CPU—and does not report any details about whether errors are detected, unlike externally-controlled ECC. Sophisticated algorithms have been built to infer the existence of corrected errors based on non-corrected errors.[21]
Subchannels
Each DDR5 DIMM has two independent channels. Earlier DIMM generations featured only a single channel and one CA (Command/Address) bus controlling the whole memory module with its 64 (for non-ECC) or 72 (for ECC) data lines. Both subchannels on a DDR5 DIMM each have their own CA bus, controlling 32 bits for non-ECC memory and either 36 or 40 data lines for ECC memory, resulting in a total number of either 64, 72 or 80 data lines. The reduced bus width is compensated by a doubled minimum burst length of 16, which preserves the minimum access size of 64 bytes, which matches the cache line size used by modern x86 microprocessors.[22]
Refreshing
DDR5 also decreased the refresh interval from 64 ms to 32 ms when operating up to 85°C. At 85°C to 95°C refresh times are 16 ms. The tRFC4 mechanism from DDR4 is retired. A tRFCsb timing is added.
It also provides two refresh commands: REFab and REFsb.
Multiple DDR5 memory chips can be mounted on a circuit board to form memory modules. For use in personal computers and servers, DDR5 memory is usually supplied in 288-pin dual in-line memory modules, more commonly known as DIMMs. As with previous memory generations, there are multiple DIMM variants available for DDR5.
Unbuffered memory modules (UDIMMs) directly expose the memory chip interface to the module connector. Registered or load-reduced variants (RDIMMs/LRDIMMs) use additional active circuitry on the memory module in order to buffer the signals between the memory controller and the DRAM chips. This reduces the capacitive load on the DDR5 bus.[citation needed]
DDR5 UDIMMs use 5V input, whereas RDIMMs and LRDIMMs use 12V.[23] In order to prevent damage by accidental insertion of the wrong memory type, DDR5 UDIMMs and (L)RDIMMs are not mechanically compatible. Additionally, DDR5 DIMMs are supplied with management interface power at 3.3V,[24][25] and use on-board circuitry (a power management integrated circuit[26] and associated passive components) to convert to the lower voltage required by the memory chips. Final voltage regulation close to the point of use provides more stable power, and mirrors the development of voltage regulator modules for CPU power supplies.[citation needed]
Operation
Standard DDR5 memory speeds range from 4,000 to 6,400 million transfers per second (PC5-32000 to PC5-51200).[3] Higher speeds may be added later, as happened with previous generations. XMP profiles currently allow 8000 MT/s with 1.400 V/1.450 V, which is much higher than 1.1 V in the JEDEC standard.
Compared to DDR4 SDRAM, the minimum burst length was doubled to 16, with the option of "burst chop" after eight transfers. The addressing range is also slightly extended as follows:
The number of chip ID bits remains at three bits, allowing up to eight stacked chips (3 → 3).
A third bank group bit (BG2) was added, allowing up to eight bank groups (2 → 3).
The maximum number of banks per bank group remains at four (2 → 2),
The number of row address bits remains at 17, for a maximum of 128K rows (17 → 17).
One more column address bit (C10) is added, allowing up to 8192 columns (1KB pages) in ×4 chips (11 → 12).
The least-significant three column-address bits (C0, C1, C2) are removed. All reads and writes must begin at a column address which is a multiple of 8 (3 → 0). This is necessary due to the internal ECC.
One bit is reserved for addressing expansion as either a fourth chip ID bit (CID3) or an additional row address bit (R17) (0 → 1).
The command encoding was significantly rearranged and takes inspiration from that of LPDDR4; commands are sent using either one or two cycles with 14-bit bus. Some simple commands (e.g. precharge) take one cycle, while any that include an address (activate, read, write) use two cycles to include 28 bits of information.
Also like LPDDR, there are now 256 8-bit mode registers, rather than eight 13-bit mode registers. Also, rather than one register (MR7) being reserved for use by the registered clock driver chip, a complete second bank of mode registers is defined (selected using the CW bit).
The "Write Pattern" command is new for DDR5; it is similar to a normal write command, but instead of taking data from the bus, the range is filled in with copies of a one-byte mode register (which defaults to all-zero) instead of individual data. While this takes just as long to complete as a normal write, it frees up the command bus for other operations.
The multi-purpose command includes various sub-commands for training and calibration of the data bus.
Support
Intel
The 12th generation Alder Lake, 13th generation Raptor Lake, as well as 14th generation Raptor Lake Refresh CPUs support both DDR5 and DDR4 but, usually, there are only DIMM sockets for either one or the other on a motherboard. Some mainboards with Intel's H610 chipset support both DDR4 and DDR5, but not simultaneously.[28]
Sapphire Rapids server CPUs, Core Ultra Series 1 Meteor Lake mobile CPUs, and the latest Core Ultra Series 2 Arrow Lake desktop CPUs all exclusively support DDR5 and Arrow Lake also supports CUDIMM DDR5 memory standard that allows for higher default speed of 6400 MT/s.
AMD
DDR5 and LPDDR5 are supported by the Ryzen 6000 series mobile APUs, powered by their Zen 3+ architecture. Ryzen 7000 and Ryzen 9000 series desktop processors also support DDR5 memory as standard.[29]
Epyc fourth-generation Genoa and Bergamo server CPUs have support for 12-channel DDR5 on the SP5 socket.[30][31]
Notes
↑64 GB/s assumes 8 GT/s, each with 64 bits of bus width, then divided by 8 to convert from bits to bytes.
References
↑Here, K, M, G, or T refer to the binary prefixes based on powers of 1024.
↑Dr. Ian Cutress (October 6, 2020). "Insights into DDR5 Sub-timings and Latencies". AnandTech. Archived from the original on October 6, 2020. In terms of single access latency, we are ultimately not going to be any faster than we were by the end of the DDR3 era. DDR3-1866 at CL13 was already at 13.93 nanoseconds.
↑Patel, M.; Kim, J.S.; Hassan, H.; Mutlu, O. (2019). Understanding and Modeling On-Die Error Correction in Modern DRAM: An Experimental Study Using Real Devices. 2019 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN). Portland, Oregon, US. pp.13–25. doi:10.1109/DSN.2019.00017.
↑"DDR5 SDRAM RDIMM Based on 16Gb M-die"(PDF). SK Hynix. p.7. Archived from the original(PDF) on October 29, 2021. Retrieved October 29, 2021. VIN_BULK[:] 12 V power input supply pin to the PMIC. VIN_MGMT[:] 3.3 V power input supply pin to the PMIC for VOUT_1.8V & VOUT_1.0V LDO output, side band management access, internal memory read operation.
↑USpatent 10769082,Patel, Shwetal Arvind; Zhang, Andy& Meng, Wen Jieet al.,"DDR5 PMIC Interface Protocol and Operation",published November 7, 2019, assigned to Integrated Device Technology
